This invention concerns a CMOS gate array and, more specifically, it relates to a basic cell structure constituting a circuit.
The CMOS gate arrays have advantages in that their power consumption is extremely low and the degree of integration can be increased but, there is a disadvantage in that the operation speed is lower as compared with TTL or ECL gate array.
FIG. 1 shows the basic structure of a gate array, in which the chip plane can be divided into a wiring region 1 and basic cell regions 2. In the wiring region 1, first layer metal wirings 3, are usually formed in the horizontal direction (shown by the solid line in the drawing), the second layer metal wirings, 4, are formed in the vertical direction (shown the dotted chain in the drawing), and electrical contacts are established at the crossing points of the wirings by way of through holes. The second layer metal wirings 4 are arranged such that they can be laid along the vertical direction on the basic cell regions 2, and can be connected with other wiring in region 1.
Each of the basic cell regions 2 comprises basic cells 20, each having the identical substrate structure which are disposed side by side along the horizontal direction in the drawing. In the case of a 2-input gate basic cell, ech cell requires five second layer metal wirings including two input terminals 41, 42, one output terminal 43 and two wires situated on the basic cell region. In the ordinary design of the gate array the configuration of the basic cell is restricted by the second layer metal wirings as described later.
FIG. 2 shows a basic cell structure where the basic cell 20 shown in FIG. 1 is constituted as a 2-input gate array using CMOSs. In the figure, a region, 5, for a P channel MOS transistor defined with the length L1 and the width Wp and a region 6 for a N channel MOS transistor defind with the legth L1 and the width Wn are disposed in pair. Those regions 51, 52, 53 and 61, 62, 63, divided by the solid lines in the regions 5 and 6, represent respectively diffusion regions for forming each of the transistors. Polysilicon gates 71, 72, 81, 82 are disposed by way of a gate insulating film on a substrate between each of the adjacent diffusion regions 51 and 52, 52 and 53, 61 and 62, and 62 and 63. In the figure, the mark X indicated at one end for each of the polysilicon gate electrodes represents a contact for the connection between each of the polysilicon gates 71, 72, 81 and 82 and the first layer metal wirings. Furthermore, contacts 91-96 and 101-106 are disposed to the respective regions diffusion regions 51, 52, 53, 61, 62 and 63 as required in order to make electrical connection with the first layer metal wirings. In the drawing, VCC and GND lines shown by the broken line represent the first metal wirings for the power source line. Further, the marks "o", 111-116, shown in the wiring region represent through holes between the first layer metal wiring 3 and the second layer metal wiring 4. The second layer metal wirings are formed in a direction parallel to polysilicon gates 71, 72, 81, 82.
The conventional CMOS gate array comprising the cell structure as described above has a restriction in that the lateral size Li of the cell is generally determined by the pitch x, the number of the second layer metal wirings where the length L1 is dependent upon the number of second layer metal wirings in the gate array. In the case where the cell size is determined depending on the second layer metal wirings as described above, there are problems in that excess space is left in view of the design rule with respect to the diffusion region 5 constituting the transistor in the basic cell regions 2 or near the contact portion between the polysilicon gates and the first layer metal wirings in the wiring region 1, hindering effective utilization of the substrate. Also, the inherent defect of the CMOS, that its operational speed is slow, cannot be prevented in the circuit constituted with the conventional cell structure.